1. Field of the Invention
The present invention relates to a thin film transistor panel for use in an active matrix liquid crystal display and a driving circuit for driving a photosensor.
2. Description of the Related Art
FIG. 11A is a plan view showing one of first conventional thin film transistors of a panel for use in an active matrix liquid crystal display and FIG. 11B is a cross-sectional view of the thin film transistor taken along the line 11B--11B in FIG. 11A.
A gate line 2 and a gate electrode 2a, extending from the gate line 2, are formed on a transparent glass substrate 1. The gate line 2 and the gate electrode 2a are covered by a gate insulating film 3. An amorphous silicon layer 4 and a transparent pixel electrode 8 for applying a driving voltage to a liquid crystal are formed on the gate insulating film 3. A central portion of the amorphous silicon layer 4 is covered by a protecting layer 5 formed of an insulating film or metal. A first end of the amorphous silicon layer 4 is connected to a drain electrode 6a extending from a drain line 6 and a second end of the amorphous silicon layer 4 is connected to a source electrode 7. The source electrode 7 is connected to the pixel electrode 8 formed on the gate insulating film. In this structure, that region of the amorphous silicon layer 4, corresponding to the protecting layer 5, functions as a channel region. Since the amorphous silicon layer 4 and the protecting layer 5 have different shapes, different photomasks must be used in etching. For this reason, a great number of steps are required in the manufacturing process, with the result that the manufacturing yield is reduced. In addition, due to positional deviation in mask alignment for forming the amorphous silicon layer 4, a width W' of the protecting layer 5 and the gate electrode 2a must be considerably wider than a width W of the amorphous silicon layer 4 (in general, the width W' is at least 10 micron wider than the width W). The area of the pixel electrode 8 is therefore reduced, resulting in a low opening ratio.
FIGS. 12A and 12B show another conventional art. The structure of this conventional art is different from the above-mentioned first conventional art, only in that the amorphous silicon layer 4 exists in an overall region in which the protecting layer 5 is formed. In other words, the channel region of the amorphous silicon layer 4 has the same width and shape as those of the protecting layer 5. In this structure, when the protecting layer 5 is formed by means of etching, the channel region of the amorphous silicon layer 4 is completely covered. However, since the channel region of the amorphous silicon layer 4 is wide, a gate-source parastic capacitance C.sub.gs is inevitably great. When the gate-source parastic capacitance C.sub.gs is increased, a pixel capacitance maintained between the pixel electrode 8 and a liquid crystal (not shown) is varied, with the result that the display quality is degraded. The number of steps of the manufacturing process and the occupation ratio of the thin film transistor are the same as those in the first conventional art.